Semiconductor device and wiring tape for semiconductor device

ABSTRACT

In a semiconductor device having a three-layered buffer layer comprising core layer  1  having interconnected foams such as a three-dimensional reticular structure and adhesive layers  2  proved on both sides of the core layer as a stress buffer layer between semiconductor chip  5  and wiring  4  to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer  1  to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semi-conductor device for usein high density-packaged modules, multichip modules, etc. and a wiringtape for use in preparation of the semiconductor device.

[0002] With recent trends to make electronic devices smaller in scaleand higher in performance, a higher degree of integration, a higherdensity and a higher processing speed have been required for thesemiconductor devices for use therein. Correspondingly, packagingprocedures for the semiconductor devices have been also shifted from thepin insertion type towards the surface mount type. To meet higher pincounts, packages including DIP (dual inline package), QFP (quad flatpackage), PGA (pin grid array), etc. have been also developed.

[0003] However, QFP is provided with concentrated connection leads to apackage substrate only at the peripheral region of the package and theleads per se are so fine that they are liable to deform, resulting indifficulty in packaging to meet the trend for higher pin counts. PGA haslong and fine and highly dense terminals for connection to a packagesubstrate, resulting in difficulty in realization of higher speed, andalso is of a pin insertion type and thus incapable of attain surfacepackaging. That is, PGA has no advantage in case of high densitypacking.

[0004] To solve these problems and realize semiconductor devices capableof meeting higher speed requirements, a BGA (ball grid array) packagehaving a stress buffer layer between the semiconductor chip and thewiring layer and also having ball-like connection terminals on thepackage substrate-facing side of the wiring layer has been recentlydeveloped (U.S. Pat. No. 5,148,265). In the package with this structure,the terminals for connection to the package substrate are of a ball-likesolder, and thus there is no such lead deformation as in case of QFP,and distribution of terminals all over the package surface enables tomake interterminal pitches larger and surface packaging easier.Furthermore, the connection terminals are shorter than those of PGA, andthus inductance components are smaller with accelerated signal speed,thereby enabling to meet the higher speed requirements.

[0005] For the stress buffer layer in the BGA package, an elastomer isused. Specifically, the stress buffer layer for a semiconductor deviceis provided in such a package structure comprising a wiring layer with awiring formed on a support made from such an insulating material aspolyimide, etc.; an elastomer of low elasticity such as silicone, etc.,formed on the wiring layer; a semiconductor chip; and a substrate forheat radiation and for supporting a semiconductor device. Elastomer forthe buffer layer can be formed by printing using a metal mask or bypasting a sheet-like elastomer. For formation of the buffer layer byprinting, the following four steps are required: printing, heat curing,adhesive application and chip pasting. A heat set type, siliconeelastomer material, when used, brings about such a problem ascontamination of the wiring layer, packaging apparatuses, etc. due toevaporated components, etc. during the curing, thereby deteriorating thereliability in electrical connection between the semiconductor chip andthe leads, when made therebetween. In pasting sheet-like elastomer,steam explosion due to steam absorbed during the package reflow occurs,thereby bringing about such problems as expansion of the package andpeeling of the wiring layer.

SUMMARY OF THE INVENTION

[0006] An object of the present invention is to provide a semiconductordevice having a high reliability and extremely less occurrence offailure at the package reflow in the above-mentioned semiconductorpackage structure.

[0007] According to a first aspect of the present invention, there isprovided a semiconductor device, which comprises a semiconductor chiphaving a circuit-formed surface provided with a group of terminalsthereon; a wiring layer comprising an insulating layer and a wiring forconnecting the group of terminals to a group of external terminalsprovided on the surface of the insulating layer, the surface facing thecircuit-formed surface of the semiconductor chip; a three-layered bufferlayer provided between the circuit-formed surface of the semiconductorchip and the wiring layer, the buffer layer comprising a structurehaving interconnected foams, an adhesive layer provided on thesemiconductor chip-facing side of the structure having interconnectedfoams, directed to pounding to the semiconductor chip and anotheradhesive layer provided on the other side of the structure, directed tobonding to the wiring layer; a sealant for sealing connections of thegroup of terminals provided on the semiconductor chip to the wiringlayer; and the group of external terminals connected to the wiringlayer.

[0008] According to a second aspect of the present invention, there isprovided a wiring tape for a semiconductor device, which comprises awiring layer comprising an insulating layer and a wiring on aninsulating layer, one end of the wiring being connected to terminals onthe semiconductor chip and the other end of the wiring being connectedto external terminals for connecting to a package substrate; and athree-layered buffer layer bonded to the wiring-provided side of thewiring layer, the buffer layer comprising a structure havinginterconnected foams, an adhesive layer provided on the semiconductorchip-facing side of the structure having interconnected foams, directedto ponding to the semiconductor chip and another adhesive layer providedon the other side of the structure, directed to bonding to the wiringlayer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a graph showing relations between the thickness ratio ofcore layer to total buffer layer and the failure rate at package reflow.

[0010]FIGS. 2A and 2B show a semiconductor device according to oneembodiment of the present invention, where

[0011]FIG. 2A is a schematic cross-sectional view thereof and

[0012]FIG. 2B is a bottom plan view thereof.

[0013]FIG. 3 is a schematic cross-sectional view of a semiconductordevice according to another embodiment of the present invention.

[0014]FIGS. 4A and 4B show a semiconductor device according to a furtherembodiment of the present invention, where

[0015]FIG. 4A is a schematic cross-sectional view thereof and FIG.

[0016]4B is a bottom plan view thereof.

[0017]FIG. 5 shows a semiconductor device according to a still furtherembodiment of the present invention.

[0018]FIGS. 6A to 6F are schematic views showing steps of preparing awiring tape according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The present semiconductor device has a three-layered buffer layercomprising a core layer in a structure having interconnected foams andadhesive layers provided on both sides of the core layer, respectively,to lessen a thermal stress generated between a semiconductor chip and apackage substrate. The conventional procedure for forming a stressbuffer layer by printing requires 4 steps from the elastomer formationto chip pasting, whereas use of the present three-layered buffer layercan reduce the number of steps to 2, and since the core layer is in agas-permeable structure having interconnected foams, steam pressuregenerated at package reflow can be released to the outside through thecore layer, thereby preventing expansion or peeling of the wiring layer.

[0020] The present invention provides a semiconductor device, whichcomprises a semiconductor chip having a circuit-formed surface providedwith a group of terminals thereon; a wiring layer comprising aninsulating layer and a wiring for connecting the group of terminals to agroup of external terminals provided on the surface of the insulatinglayer, the surface facing the circuit-formed surface of thesemiconductor chip; a three-layered buffer layer provided between thecircuit-formed surface of the semiconductor chip and the wiring layer,the buffer layer comprising a structure having interconnected foams as acore layer, an adhesive layer provided on the semiconductor chip-facingside of the structure having interconnected foams, directed to bondingto the semiconductor chip and another adhesive layer provided on theother side of the structure, directed to the wiring layer; a sealant forsealing connections of the group of terminals provided on thesemiconductor chip to the wiring layer; and the group of externalterminals connected to the wiring layer.

[0021] The buffer layer comprises a core layer in a structure havinginterconnected foams, and adhesive layers provided on both sides of thecore layer, respectively, where a thickness ratio of the core layer tothe total buffer layer is preferably at least 0.2. The structure havinginterconnected foams means a porous body having a large number of poresand includes a three-dimensional reticular structure. The structurehaving interconnected foams can be a non-woven fabric formed fromthree-dimensionally entangled fibrous compounds. The semiconductor chipcan be a silicon chip having a semiconductor circuit formed on a siliconwafer by a desired process such as logic, memory, gate array, etc. Thepresent semiconductor device can be provided with a heat radiation,support substrate on the opposite surface of the semiconductor chip tothe circuit-formed surface. The support substrate can be made frommetals such as aluminum, iron, nickel, tungsten, etc. or alloys of atleast two of these metals in combination or ceramic materials such asalumina, etc. The opposite surface of the support substrate may beprocessed into a fin shape to maximize the surface area and enhance theheat radiation.

[0022] The present semiconductor device can be also provided in thefollowing embodiments.

[0023] A) A semiconductor device, which comprises a semiconductor chiphaving a circuit-formed surface provided with a group of terminalsthereon; a support substrate covering an opposite surface of thesemiconductor chip to the circuit-formed surface and side ends of thesemiconductor chip; a wiring layer comprising an insulating layer and awiring for connecting the group of terminals to a group of externalterminals provided on the surface of the insulating layer, the wiringlayer being provided on the side facing the circuit-formed surface ofthe semiconductor chip and extended over to the support substrate; athree-layered buffer layer provided between both of the circuit-formedsurface of the semiconductor chip and the support substrate and thewiring layer, the buffer layer comprising a structure havinginterconnected foams, an adhesive layer provided on the semiconductorchip-facing side of the structure having interconnected foams, directedto bonding to the semiconductor chip and another adhesive layer providedon the other side of the structure, directed to bonding to the wiringlayer; a sealant for sealing connections of the group of terminalsprovided on the semiconductor chip to the wiring layer; and the group ofexternal terminals connected to the wiring layer, positioned on thesupport substrate.

[0024] B) A semiconductor device, which comprises a semiconductor chiphaving a circuit-formed surface provided with a group of terminalsthereon; a support substrate covering an opposite surface of thesemiconductor chip to the circuit-formed surface and side ends of thesemiconductor chip; a wiring layer comprising an insulating layer and awiring for connecting the group of terminals to a group of externalterminals provided on the surface of the insulating layer, the wiringlayer being provided on the side facing the circuit-formed surface ofthe semiconductor chip and extended over to the support substrate; athree-layered buffer layer provided between both of the circuit-formedsurface of the semiconductor chip and the support substrate and thewiring layer, the buffer layer comprising a structure havinginterconnected foams, an adhesive layer provided on the semiconductorchip-facing side of the structure having interconnected foams, directedto bonding to the semiconductor chip and another adhesive layer providedon the other side of the structure, directed to bonding to the wiringlayer; a sealant for sealing connections of the group of terminalsprovided on the semiconductor chip to the wiring layer; and the group ofexternal terminals connected to the wiring layer, positioned within theregion of the semiconductor chip and on the support substrate.

[0025] In the above-mentioned semiconductor devices with variousmodifications, the group of terminals provided on the surface of thesemiconductor chip may be arranged in one direction on the centralregion on the circuit-formed surface of the semiconductor chip, or maybe arranged in the peripheral region on the circuit-formed surface ofthe semiconductor chip. Further, the group of external terminals may bearranged within the region of the semiconductor chip.

[0026] Further, the wiring layer may be provided with a window at aposition of connection to the group of terminals on the semiconductorchip. In addition, extensions of the wiring in the wiring layer may beconnected to the group of terminals provided on the semiconductor chip.

[0027] The present invention can be also provided in the followingembodiment:

[0028] A wiring tape for a semiconductor device, which comprises awiring layer comprising an insulating layer and a wiring on theinsulating layer, one end of the wiring being connected to terminals onthe semiconductor chip and the other end of the wiring being connectedto external terminals for connecting to a package substrate; and athree-layered buffer layer bonded to the wiring-formed side of thewiring layer, the buffer layer comprising a structure havinginterconnected foams as a core layer, an adhesive layer provided on thesemiconductor chip-facing side of the structure having interconnectedfoams, directed to the semiconductor chip and another adhesive layerprovided on the other side of the structure, directed to bonding to thewiring layer.

[0029] The present wiring tape comprises a conductor layer, i.e. awiring, an insulating layer and a stress buffer layer, where the stressbuffer layer comprises a core layer composed of an interconnected foamstructure and adhesive layers provided on both sides of the core layer,respectively, and a thickness ratio of the core layer to the entirestress buffer layer is preferably at least 0.2.

[0030] The interconnected foam structure of the wiring tape can be madeof non-woven fabric of three-dimensionally entangled fibrous compounds.The insulating layer of the wiring tape can be preferably made ofengineering plastics having a high heat resistance and distinguishedmechanical characteristics such as polyimide, etc. The conductor layer,i.e. wiring, can be formed from gold, copper, aluminum or their topsurface-gold plated ones by patterning. The wiring tape may be furtherprovided with a ground layer or a power source layer besides the wiringin view of its electrical characteristics.

[0031] External terminals for electrical connection between a packagesubstrate and a semiconductor device mounted thereon is a heat-meltable,electrically connectable electric conductor. The external terminals canelectrically connect the semiconductor device to the package substrateby shaping solder alloys containing tin, zinc or lead, silver, copper oralloy into ball-like shapes or in case of other materials than gold bycoating them with gold beforehand, followed by bringing the balls intocontact and vibration with or without heat melting. Besides theabove-mentioned structure of external terminals, ball-like terminals maybe in such a structure made of one of molybdenum, nickel, copper,platinum, titanium, etc. or alloys of at least two thereof incombination, or at least two of these metals and metallic alloys as amultilayered film.

[0032] The adhesive layers for use in the buffer layer in the wiringtape and the semiconductor device can be made from either athermoplastic resin or a thermosetting resin, in a simple resinstructure composed of such resins as epoxy resin, maleimide resin,phenol resin, cyanate resin, resol, polyamide, polyimide,polyamide-imide, polyester, polyolefin, polyurethane, etc. or theirmixtures. Besides the above-mentioned resins, materials capable ofshowing an adhesiveness upon heating, drying, pressuring, lightirradiation, etc. can be used. Furthermore, the adhesive layers may bein a sheet-like structure such as cloth-like core materials, etc.impregnated with the above-mentioned resins besides the simple resinstructure.

[0033] Materials for use in the core layer used in the structure havinginterconnected foams in the semiconductor device and the wiring tape caninclude such resin as polycarbonate, polyester,polytetraflouoroethylene, polyethylene, polypropylene, polyvinylidenefluoride, cellulose acetate, polysulfone, polyacrylonitrile, polyamide,polyimide, etc., and a fluorine-containing resin is preferably used.Three-dimensional reticular structure with fine pores can be formed bytreating these materials by a track etching process based on neutronirradiation and chemical etching; a stretching process based onstretching of crystalline polymers after heating or plasticization witha plasticizer; a molten layer separation process based on use ofsolvents having different solubilities depending on temperatures; anextraction process based on mixing of the polymers with an inorganicsalt or silica, followed by film formation and extraction only of theinorganic salt or silica; or a layer transfer process based on mixingthe polymers with a good solvent, a poor solvent, etc., followed by filmformation and successive drying off only the good solvent. Non-wovenfabrics are sheets of these resins in fiber forms obtained bypolymerization in a solvent. Any interconnected foam structure can beused as core layer besides the above-mentioned ones, so long as it has agas permeability.

[0034] A buffer layer sheet having a stress buffer mechanism or athree-layered buffer layer can be prepared by coating or pasting bothsides of the core layer with adhesive layers or sheet-like adhesivelayers, respectively. Alternatively, the buffer layer may be composed bya laminate obtained by pasting the adhesive layers filled with anadhesive into pores of an interconnected foam structure on both sides ofthe structure having interconnected forms, respectively. As a result ofinvestigation on relations between the core layer thickness ratio andthe reliability for semiconductor device packaging, it has been founddesirable that a thickness ratio of the core layer to the entire bufferlayer is at least 0.2.

[0035]FIG. 1 is a graph showing relations between a thickness ratio ofthe core layer to the entire buffer layer and a failure rate at packagereflow, where a ratio (a/b) of thickness (a) of core layer 1 to totalthickness (b) of buffer layer (i.e. sum total of thickness of core layer1 and thickness of adhesive layers 2) is plotted on the abscissa and afailure rate at the package reflow is plotted on the ordinate. Reflowtests were carried out with test pieces of semiconductor device packagesusing buffer layer sheets with total thicknesses (b) of core layer andadhesive layers being 100 μm, 150 μm and 200 μm by leaving the testpieces in a circumstance at a temperature of 85° C. and a relativehumidity of 85% for 168 hours to allow the test pieces to absorb themoisture, then heating the test pieces up to 160° C. at a rate of 5°C./second, keeping at 160° C. for 60 seconds, then heating again up to240° C. at a rate of 5° C./second, and keeping at 240° C. for 5 seconds,following by cooling.

[0036] It can been seen from FIG. 1 that the failure rate increasesabruptly in a core layer thickness ratio (a/b) of less than 0.2. Thatis, the package reliability of the present semiconductor device can bedrastically improved by making the core layer thickness ratio (a/b) ofthe buffer layer having a stress buffer mechanism at least 0.2. Thepresence of the core layer can release the steam pressure even uponheating the moisture-absorbed semiconductor device at the packagereflow, thereby preventing the semiconductor device from breaking andimproving the package reliability. The core layer has desirably athickness of 80 to 200 μm. By making the thickness of core layer notless than 80 μm, a sag can be given to leads connecting to thesemiconductor chip terminals, thereby making breaking of leads less.Above 200 μm, the buffer effect will be reduced. The adhesive layershave preferably a thickness of 1 to 30 μm. That is, the presentsemiconductor device has a buffer layer having a stress buffer mechanismin a three-layered structure comprising a core layer of interconnectedfoam structure (i.e. core layer capable of releasing steam pressure) andadhesive layers provided on both sides of the core layer, respectively,where a ratio (a/b) of core layer thickness (a) to total thickness (b)of buffer layer is made not less than 0.2.

[0037] According to the present invention, a thermal stress developedbetween the semiconductor device and the package substrate can belessened by the buffer layer provided between the semiconductor chip andthe wiring layer. Furthermore, the production process can be simplifiedby using a buffer layer of three-layered structure comprising a corelayer of interconnected foam structure and adhesive layers provided onboth sides of the core layer, respectively, thereby improving the massproduction capacity. No such heat set type silicone materials are usedfor the core layer and thus the semiconductor chip can be prevented fromcontamination at heat setting. Furthermore, steam pressure at thepackage reflow can be released through the porous core layer ofthree-dimensional reticular structure, etc., thereby preventing thewiring layer from expansion or peeling, and thus a semiconductor devicehaving a high package reliability can be obtained.

[0038] In this connection, JP-A 2-49544 (=EP160439) and JP-A 4-363032(=EP504669) disclose similar structures to that of the present stressbuffer layer, but JP-A 2-49544 is directed to a printed substrate andJP-A 4-363032 is directed to quite a different semiconductor devicestructure from that of the present invention.

[0039] Embodiments according to the present invention will be describedin detail below, referring to Examples and Drawings.

EXAMPLE 1

[0040]FIGS. 2A and 2B shows a semiconductor device according to oneembodiment of the present invention, where FIG. 2A is a schematiccross-sectional view of the present semiconductor device and FIG. 2B abottom plan view thereof. The semiconductor device was preparedaccording to the following steps.

[0041] Long polyimide film 3 (Upilex, trademark of a productcommercially available from Ube Industries, Ltd., Japan), 38 mm wide and50 μm thick, coated with an epoxy-based adhesive was punched to form awindow (1.5 mm×8 mm) for chip connection. Then, an electrolytic copperfoil, 18 μm thick, was pressure-rolled onto the polyimide film with aroller heated at 150° C. Then, a photosensitive resist (P-RS 300S,identification mark of a product commercially available from Tokyo OhkaKogyo Co., Ltd., Japan) was applied to the rolled copper foil, thenbaked at 90° C. for 30 minutes and subjected to light exposure through apattern, followed by development, thereby forming an etching mask. Then,the copper was etched with iron chloride at 40° C. and then the resistwas removed by peeling to form a copper wiring. The wiring waselectrically gold-plated to obtain a wiring substrate (wiring layer)with gold-plated wiring 4.

[0042] On the other hand, a thermoplastic polyetheramide-imide varnish(HM-1, identification mark of a product commercially available fromHitachi Chemical Co., Ltd., Japan) was applied to a thickness of 30 μmonto both sides of polytetrafluoroethylene core layer 1 having athree-dimensional reticular structure, 150 μm thick, prepared accordingto a stretching process, each to a thickness of 30 μm, followed bydrying to prepare an adhesive sheet (buffer layer) having adhesivelayers 2 on both sides. The adhesive sheet had core layer 1 soaking theadhesive to a depth of about 10 μm. The adhesive sheet was punched to adesired shape on a die, and then pressure-rolled onto the wiringsubstrate with heating at 250° C. for 2 seconds to prepare a wiringtape.

[0043] Semiconductor chip 5 having a group of aluminum terminalsarranged in one direction in the central region on the circuit-formedsurface was pasted with the wiring tape at 250° C. for 2 seconds bypositioning. Then, leads 6 protruded from the wiring layer wereconnected to aluminum pads 18 as terminals of the semiconductor chip byapplying ultrasonic waves thereto. The connected terminal region wassealed with silicone-based sealant 7 (TSJ 3150, identification mark of aproduct commercially available from Toshiba Silicone Co., Ltd., Tokyo)and heat set at 150° C. for 4 hours. A flux was applied to the externalterminal connection region of the wiring layer, and eutectic solderballs (Pb 63: Sn 37), 0.6 mm in diameter, were placed thereon andsubjected to IR reflow heating at 240° C. for 5 seconds to form solderball connection terminals 8.

[0044] The semiconductor device so prepared is prevented from expansionor peeling of the wiring layer because the steam can be released fromthe side ends of porous buffer layer and has such an advantage that theadhesive layers can attain adhesion for a short time because it is madefrom a thermoplastic resin. Furthermore, the wiring layer and the bufferlayer are provided with a common window, through which a sealant can befilled to attain sealing, and thus sealing can be made easily andassuredly. Still furthermore, leads protruded from the wiring layer aredirectly connected to terminals of semiconductor chip, and thus there isno necessity for using any additional connection members. Stillfurthermore, use of the adhesive sheet can simplify the productionprocess and thus the mass production capacity can be improved.

[0045] The semiconductor device having solder ball connection terminalswithin the semiconductor chip area prepared according to the foregoingsteps was subjected to moisture absorption in a circumstance at atemperature of 85° C. and a relative humidity of 85% for 48 hours andthen to a reflow test under the same conditions as those for obtainingthe data as shown in FIG. 1. Furthermore, the time required from thebuffer layer formation to the chip pasting was measured. Stillfurthermore, a connection failure rate in connecting the leads to thesemiconductor chip was evaluated. Results are shown in Table 1. Noconnection failure was detected.

EXAMPLE 2

[0046]FIG. 3 is a schematic cross-sectional view of a semiconductordevice according to another embodiment of the present invention. Thesemiconductor device was prepared according to the following steps.

[0047] Long polyimide film 3 (Upilex, trademark of a productcommercially available from Ube Industries, Ltd., Japan), 38 mm wide and50 μm thick, coated with an epoxy-based adhesive was punched to form awindow (1.5 mm×8 mm) for chip connection. Then, an electrolytic copperfoil, 18 μm thick, was pressure-rolled onto the polyimide film with aroller heated at 150° C. Then, a photosensitive resist (P-RS300S,identification mark of a product commercially available from Tokyo OhkaKogyo Co., Ltd., Japan) was applied to the rolled copper foil, thenbaked at 90° C. for 30 minutes and subjected to light exposure through apattern, followed by development, thereby forming an etching mask. Then,the copper was etched with iron chloride at 40° C. and then the resistwas removed by peeling to form a copper wiring. The wiring waselectrically gold-plated to obtain a wiring substrate (wiring layer)with gold-plated wiring 4.

[0048] A varnish of a thermosetting epoxy resin (YX-4000, identificationmark of a product commercially available from Yuka-Shell Epoxy K.K.,Japan) in a methyl ethyl ketone solvent, admixed with an o-cresolnovolak curing agent (H-1, identification mark of a product commerciallyavailable from Meiwa Plastic Industries, Ltd., Japan) and further with afine silica filler (R974, identification mark of a product commerciallyavailable from Nippon Aerosil Co., Ltd., Japan), nitrobutadiene rubber(XER-91, identification mark of a product commercially available fromJapan Synthetic Rubber Co., Ltd., Japan) and an epoxy-curing catalystcomposed of triphenylsulfone (TPP, identification mark of a productcommercially available from Wako Pure Chemical Industries, Ltd., Japan)was applied to both sides of polyimide core layer 1 (thickness: 120 μm)having a three-dimensional reticular structure, prepared according to alayer transfer process, each to a thickness of 30 μm, followed by dryingto prepare adhesive layers, each 30 μm thick. An adhesive sheet (bufferlayer) having adhesive layers 2 on both sides, obtained by pasting thecore layer with the adhesive layers on both sides through a rolllaminator, was punched to a desired shape on a die and pressure-rollonto the wiring substrate having the patterned wiring with heating at120° C. for 2 seconds to form a wiring tape.

[0049] Semiconductor chip 5 having a group of terminals arranged in theperipheral region on the circuit-formed surface was pasted with thewiring tape at 120° C. for 2 seconds by positioning. Then, leads 6protruded from the wiring layer were connected to aluminum pads 18 asterminals of the semiconductor chip by applying ultrasonic wavesthereto. The connected terminal region was sealed with epoxy-basedsealant 7 (RC021C, identification mark of a product commerciallyavailable from Hitachi Chemical Co., Ltd., Japan) and heat set at 80° C.for 30 minutes and at 150° C. for 4 hours. A flux was applied to thesolder ball connection region of the wiring layer, and eutectic solderballs (Pb 63: Sn 37), 0.6 mm in diameter, were placed thereon andsubjected to IR reflow heating at 240° C. for 5 seconds to form solderball connection terminals 8. The semiconductor device of this structurehas, in addition to the effects as obtained in Example 1, a such furthereffect that the adhesive sheet (buffer layer) can attain adhesion to thesemiconductor chip at a relatively low temperature, because thethermosetting resin is used as an adhesive for the buffer layer.

[0050] The semiconductor device prepared according to the foregoingsteps was subjected to moisture absorption in a circumstance at atemperature of 85° C. and a relative humidity of 85% for 48 hours andthen to a reflow test under the same conditions as those for obtainingthe data as shown in FIG. 1. Furthermore, the time required from thebuffer layer formation to the chip pasting was measured. Stillfurthermore, a connection failure rate in connecting the leads to thesemiconductor chip was evaluated. Results are shown in Table 1.

EXAMPLE 3

[0051]FIGS. 4A and 4B show a semiconductor device according to a furtherembodiment of the present invention, where FIG. 4A is a schematiccross-sectional view thereof and FIG. 4B is a bottom plan view thereof.The present semiconductor device was prepared according to the followingsteps.

[0052] Long polyimide film 3 (Upilex, trademark of a productcommercially available from Ube Industries, Ltd., Japan), 38 mm wide and50 μm thick, coated with an epoxy-based adhesive was punched to form 4windows (1.5 mm×8 mm for each) for chip connection. Then, anelectrolytic copper foil, 18 μm thick, was pressure-rolled onto thepolyimide film with a roller heated at 150° C. Then, a photo-sensitiveresist (P-RS 300S, identification mark of a product commerciallyavailable from Tokyo Ohka Kogyo Co., Ltd., Japan) was applied to therolled copper foil, then baked at 90° C. for 30 minutes and subjected tolight exposure through a pattern, followed by development, therebyforming an etching mask. Then, the copper was etched with iron chlorideat 40° C. and then the resist was removed by peeling to form a copperwiring. The wiring was electrically gold-plated to obtain a wiringsubstrate (wiring layer) with gold-plated wiring 4.

[0053] A varnish of a thermosetting epoxy resin (YX-4000, identificationmark of a product commercially available from Yuka-Shell Epoxy K.K.,Japan) in a methyl ethyl ketone solvent, admixed with an o-cresolnovolak curing agent (H-1, identification mark of a product commerciallyavailable from Meiwa Plastic Industries, Ltd., Japan) and further with afine silica filler (R974, identification mark of a product commerciallyavailable from Nippon Aerosil Co., Ltd., Japan), nitrobutadiene rubber(XER-91, identification mark of a product commercially available fromJapan Synthetic Rubber Co., Ltd., Japan) and an epoxy-curing catalystcomposed of triphenylsulfone (TPP, identification mark of a productcommercially available from Wako Pure Chemical Industries, Ltd., Japan)was applied to both sides of polyimide non-woven fabric core layer 1(thickness: 50 μm) prepared by a wet process each to a thickness of 30μm, followed by drying to prepare an adhesive sheet (buffer layer)having adhesive layers 2 on both sides. The adhesive sheet was punchedto a desired shape on a die, and then pressure-rolled onto the wiringsubstrate having the patterned wiring with heating at 120° C. for 2seconds to form a wiring tape.

[0054] Semiconductor chip 5 having a group of terminals arranged in theperipheral region on the circuit-formed surface was pasted with thewiring tape at 120° C. for 2 seconds by positioning and further withsemiconductor support substrate 9 under the same conditions as above.Then, leads 6 protruded from the wiring layer were connected to aluminumpads 18 as terminals of the semiconductor chip by applying ultrasonicwaves thereto. The connected terminal regions were sealed withepoxy-based sealant 7 (TSJ 3150, identification mark of a productcommercially available from Toshiba Silicone Co., Ltd., Japan) and heatset at 150° C. for 4 hours. A flux was applied to the solder ballconnection region of the wiring layer, and eutectic solder balls (Pb 63:Sn 37), 0.6 mm in diameter, were placed thereon and subjected to IRreflow heating at 240° C. for 5 seconds to form solder ball connectionterminals 8.

[0055] The semiconductor device having solder ball connection terminalsoutside the semiconductor chip region prepared according to theforegoing steps was subjected to moisture absorption in a circumstanceat a temperature of 85° C. and a relative humidity of 85% for 48 hoursand then to a reflow test under the same conditions as those forobtaining the data as shown in FIG. 1. Furthermore, the time requiredfrom the buffer layer formation to the chip pasting was measured. Stillfurthermore, a connection failure rate in connecting the leads to thesemiconductor chip was evaluated. Results are shown in Table 1.

EXAMPLE 4

[0056]FIG. 5 is a schematic cross-sectional view showing a semiconductordevice according to a still further embodiment of the present invention.The present semiconductor device was prepared according to the followingsteps.

[0057] Long polyimide film 3 (Upilex, trademark of a productcommercially available from Ube Industries, Ltd., Japan), 38 mm wide and50 μm thick, coated with an epoxy-based adhesive was punched to from 4windows (1.5 mm×8 mm for each) for chip connection. Then, anelectrolytic copper foil, 18 μm thick, was pressure-rolled onto thepolyimide film with a roller heated at 150° C. Then, a photosensitiveresins (P-RS 300S, identification mark of a product commerciallyavailable from Tokyo Ohka Kogyo Co., Ltd., Japan) was applied to therolled copper foil, then baked at 90° C. for 30 minutes and subjected tolight exposure through a pattern, followed by development, therebyforming an etching mask. Then, the copper was etched with iron chlorideat 40° C. and then the resist was removed by peeling to form a copperwiring. The wiring was electrically gold-plated to obtain a wiringsubstrate (wiring layer) with gold plated wiring 4.

[0058] An adhesive layer prepared by impregnating a 30 μm-thickpolytetrafluoroethylene film having a three-dimensional reticularstructure, prepared by a stretching process, with a varnish of epoxyresin (YX-4000, identification mark of a product commercially availablefrom Yuka-Shell Epoxy K.K., Japan) in a methyl ethyl ketone solvent,admixed with an o-cresol novolak curing agent (H-1, identification markof a product commercially available from Meiwa Plastic Industries, Ltd.,Japan) and an epoxy-curing catalyst composed of triphenylsulphone (TPP,identification mark of a product commercially available from Wako PureChemical Industries, Ltd., Japan), followed by drying, was pasted toboth sides of polytetrafluoroethylene core layer 1 (thickness: 100 μm)having a three-dimensional reticular structure, prepared by the samestretching process as above, through a roll laminator, to form anadhesive sheet (buffer layer) having adhesive layers 2 on both sides.Then, the adhesive sheet was punched into a desired shape on a die, andpressure rolled onto the wiring substrate with the patterned wiring withheating at 120° C. for 2 seconds to form a wiring tape.

[0059] Semiconductor chip 5 having a group of terminals arranged in theperipheral region on the circuit-formed surface was pasted with thewiring tape at 120° C. for 2 seconds by positioning and further withsemiconductor support substrate 9 under the same conditions as above.Then, leads 6 protruded from the wiring layer were connected to aluminumpads 18 as terminals of the semiconductor chip by applying ultrasonicwaves thereto. The connected terminal regions were sealed withepoxy-based sealant 7 (RCO21C), identification mark of a productcommercially available from Hitachi Chemical Co., Ltd., Japan) and heatset at 80° C. for 30 minutes and at 150° C. for 4 hours. A flux wasapplied to the solder ball connection region of the wiring layer, andeutectic solder balls (Pb 63: Sn 37), 0.6 mm in diameter, were placedthereon and subjected to IR reflow heating at 240° C. for 5 seconds toform solder ball connection terminals 8.

[0060] The semiconductor device having solder ball connection terminalsinside and outside the semiconductor device region prepared according tothe foregoing steps was subjected to moisture absorption in acircumstance at a temperature of 85° C. and a relative humidity of 85%for 48 hours and then to a reflow test under the same conditions asthose for obtaining the data as shown in FIG. 1. Furthermore, the timerequired from the buffer layer formation to the chip pasting wasmeasured still furthermore, a connection failure rate in connecting theleads to the semiconductor chip was evaluated. Results are shown inTable 1.

EXAMPLE 5

[0061] The present wiring tape was prepared according to the followingsteps. FIGS. 6A to 6F schematically show the steps.

[0062] (a) Long polyimide film 3 (Upilx, trademark of a productcommercially available from Ube Industries, Ltd., Japan), 38 mm wide and50 μm thick, coated with an epoxy-based adhesive was punched to formwindows for chip connection (FIG. 6A).

[0063] (b) Electrolytic copper foil 10, 18 μm thick, was pressure-rolledonto the polyimide film with a roller heated at 150° C. (FIG. 6B).

[0064] (c) A photoresist 11 (P-RS 300S, identification mark of a productcommercially available from Tokyo Ohka Kogyo Co., Ltd., Japan) wasapplied to the rolled copper foil and baked at 90° C. for 30 minutes(FIG. 6C).

[0065] (d) The resist was subjected to light exposure through a pattern,followed by development, thereby forming an etching mask (FIG. 6D).

[0066] (e) The copper was etched with iron chloride at 40° C. and thenthe resist was removed by peeling to form a copper wiring, and the topsurface of wiring was electrically gold-plated to form gold-platedwiring 4 (FIG. 6E).

[0067] (f) Wiring tape 12 with the patterned wiring so prepared wasfixed onto stage 17 heated at 250° after positioning. Longstress-buffering adhesive film 13 obtained by impregnating cloth ofpolytetrafluoroethylene resin fibers, 150 μm thick, prepared by astretching process, with a polyetheramide-imide varnish (HM-1,identification mark of a product commercially available from HitachiChemical Co., Ltd., Japan), followed by drying, was punched into adesired shape by means of a set of die 14 and punch 15, andpressure-rolled onto the wiring tape with heating for one second to formstress-buffering adhesive layer 16 (FIG. 6F).

Comparative Example 1

[0068] A semiconductor device was prepared in the same manner as inExample 1, using a stress buffer layer comprising a polyimide film corelayer, 150 μm thick, and the same adhesive layers (thickness: 30 μm) asin Example 1 on both sides of the core layer. The semiconductor devicewas subjected to moisture absorption in a circumstance at a temperatureof 85° C. and a relative humidity of 85% for 48 hours and then to areflow test under the same conditions as those for obtaining the data asshown in FIG. 1. Furthermore, the time required from the buffer layerformation to the chip pasting was measured. Still furthermore, aconnection failure rate in connecting the leads to the semiconductorchip was evaluated. Results are shown in Table 1.

Comparative Example 2

[0069] A semiconductor device was prepared in the same manner as inExample 2, using a 150 μm-thick sheet only of the same adhesive layer asused in Example 2 as a buffer layer. The semiconductor device wassubjected to moisture absorption in a circumstance at a temperature of85° C. and a relative humidity of 85% and then to a reflow test underthe same conditions as those for obtaining the data as shown in FIG. 1.Furthermore, the time required from the buffer layer formation to thechip pasting was measured. Still furthermore, a connection failure ratein connecting the leads to the semiconductor chip was evaluated. Resultsare shown in Table 1.

Comparative Example 3

[0070] A metal mask was laid on the same wiring layer as in Example 1,and a liquid, addition-type silicone elastomer having a viscosity of 900Pa·s (TSE322, identification mark of a product commercially availablefrom Toshiba Silicone Co., Ltd., Japan) was printed thereon by anurethane rubber squeeze and cured at 150° C. for one hour to form abuffer layer, 150 μm thick. A silicone-based adhesive (KE 1820,identification mark of a product commercially available from Shin-EtsuChemical Co., Ltd., Japan) was applied to the buffer layer to athickness of 30 μm by screen printing and, after positioning, pastedwith a semiconductor chip at 180° C. for one minute. Leads protrudedfrom the wiring layer were connected to aluminum pads on thesemiconductor chip. Connected terminal region was sealed with asilicone-based sealant (TSJ 3150, identification mark of a productcommercially available from Toshiba Silicone Co., Ltd., Japan), followedby heat setting at 150° C. for 4 hours. A flux was applied to solderball connection region to the wiring layer, and eutectic solder balls(Pb 63: Sn 37), 0.6 mm in diameter, were placed thereto, followed by IRreflow heating at 250° C. for 5 seconds to form solder ball connectionterminals.

[0071] The semiconductor device prepared according to the foregoingprocess was subjected to moisture absorption in a circumstance at atemperature of 85° C. and a relative humidity of 85% for 48 hours andthen to a reflow test under the same conditions as those for obtainingthe data shown in FIG. 1. Furthermore, the time required from the bufferlayer formation to the chip pasting was measured. Still furthermore, aconnection failure rate in connecting the leads to the semiconductorchip was evaluated. Results are shown in Table 1. TABLE 1 Failure rateTime required Connection failure at package from buffer rate betweenreflow layer lead and pad (Number of formation to (Number offailures/total chip pasting failure/total test number) (seconds) testnumber) Ex. 1 0/30 10 0/100 Ex. 2 0/30 10 0/100 Ex. 3 0/30 10 0/100 Ex.4 0/30 10 0/100 Comp. 28/30  10 0/100 Ex. 1 Comp. 29/30  10 0/100 Ex. 2Comp. 0/30 80+ 65/100  Ex. 3 Curing time (1 h)

[0072] The present semiconductor devices shown in Examples 1 to 4 had alow connection failure rate due to the absence of lead contamination, ascompared with the semiconductor device of Comparative Example 3 and alsohad a short processing time, and particularly no failure at the reflowtest in contrast with the semiconductor devices of Comparative Examples2 and 3.

[0073] The present semiconductor devices having a stress bufferelastomer layer have no expansion or breakage of wiring layer whenpackaged, because the core layer in the buffer layer is in aninterconnected foam structure or a three-dimensional reticular structureand thus the steam pressure generated at the package reflow can bereleased through the core layer.

What is claimed is:
 1. A semiconductor device, which comprises asemiconductor chip having a circuit-formed surface provided with a groupof terminals thereon; a wiring layer having a wiring for connecting thegroup of terminals to a group of external terminals provided on thesurface of the insulating layer, the surface facing the circuit-formedsurface of the semiconductor chip; a three-layered buffer layer providedbetween the circuit-formed surface of the semiconductor chip and thewiring layer, the buffer layer comprising a structure havinginterconnected foams, an adhesive layer provided on the semiconductorchip-facing side of the structure having interconnected foams, directedto bonding to the semiconductor chip and another adhesive layer providedon the other side of the structure, directed to bonding to the wiringlayer; a sealant for sealing connections of the group of terminalprovided on the semiconductor chip to the wiring layer; and the group ofexternal terminals connected to the wiring layer.
 2. A semiconductordevice according to claim 1, wherein the buffer layer is a laminateobtained by pasting the two adhesive layers on both sides of thestructure having interconnected foams, respectively.
 3. A semiconductordevice according to claim 1, wherein the buffer layer is a laminateobtained by pasting the adhesive layers filled with an adhesive intopores of an interconnected foam structure on both sides of the structurehaving the interconnected foams, respectively.
 4. A semiconductor deviceaccording to claim 1, wherein the structure having interconnected foamsin the buffer layer is a porous body having a three-dimensionalreticular structure.
 5. A semiconductor device according to claim 1,wherein the structure having interconnected foams in the buffer layer isa non-woven fabric of three-dimensionally entangled fibers.
 6. Asemiconductor device according to claim 1, wherein the structure havinginterconnected foams in the buffer layer is composed offluorine-containing resin.
 7. A semiconductor device according to claim1, wherein the adhesive layers in the buffer layer are composed ofthermosetting resin.
 8. A semiconductor device according to claim 1,wherein the adhesive layers in the buffer layer are composed ofthermoplastic resin.
 9. A semiconductor device according to claim 1,wherein the group of terminals provided on the surface of thesemiconductor chip are arranged in one direction on the central regionon the circuit-formed surface of the semiconductor chip.
 10. Asemiconductor device according to claim 1, wherein the set of terminalsprovided on the surface of the semiconductor chip are arranged in theperipheral region on the circuit-formed surface of the semiconductorchip.
 11. A semiconductor device according to claim 1, wherein thewiring layer is provided with a window at a position of connection tothe group of terminals on the semiconductor chip.
 12. A semiconductordevice according to claim 1, wherein extensions of the wiring in thewiring layer are connected to the group of terminals provided on thesemiconductor chip.
 13. A semiconductor device according to claim 1,wherein a semiconductor support substrate is provided on the surfaceopposite to the circuit-formed surface of the semiconductor chip.
 14. Asemiconductor device according to claim 1, wherein a thickness ratio ofthe structure having interconnected foams to total buffer layer is atleast 0.2.
 15. A semiconductor device according to claim 1, wherein thegroup of external terminals are arranged within the region of thesemiconductor chip.
 16. A semiconductor device, which comprises asemiconductor chip having a circuit-formed surface provide with a groupof terminals thereon; a support substrate covering an opposite surfaceof the semiconductor chip to the circuit-formed surface and side ends ofthe semiconductor chip; a wiring layer comprising an insulating layerand a wiring for connecting the group of terminals to a group ofexternal terminals provided on the surface of the insulating layer, thewiring layer being provided on the side facing the circuit-formedsurface of the semiconductor chip and extended over to the supportsubstrate; a three-layered buffer layer provided between both of thecircuit-formed surface of the semiconductor chip and the supportsubstrate and the wiring layer, the buffer layer comprising a structurehaving interconnected foams, an adhesive layer provided on thesemiconductor chip-facing side of the structure having interconnectedfoams, directed to bonding to the semiconductor chip and anotheradhesive layer provided on the other side of the structure, directed tobonding to the wiring layer; a sealant for sealing connections of thegroup of terminals provided on the semiconductor chip to the wiringlayer; and the group of external terminals connected to the wiringlayer, positioned on the support substrate.
 17. A semiconductor device,which comprises a semiconductor chip having a circuit-formed surfaceprovided with a group of terminals thereon; a support substrate coveringan opposite surface of the semiconductor chip to the circuit-formedsurface and side ends of the semiconductor chip; a wiring layercomprising an insulating layer and a wiring for connecting the group ofterminals to a group of external terminals provided on the surface ofthe insulating layer, the wiring layer provided on the side facing thecircuit-formed surface of the semiconductor chip and extended over tothe support substrate; a three-layered buffer layer provided betweenboth of the circuit-formed surface of the semiconductor chip and thesupport substrate and the wiring layer, the buffer layer comprising astructure having interconnected foams, an adhesive layer provided on thesemiconductor chip-facing side of the structure having interconnectedfoams, directed to bonding to the semiconductor chip and anotheradhesive layer provided on the other side of the structure, directed tobonding to the wiring layer; a sealant for sealing connections of thegroup of terminals provided on the semiconductor chip to the wiringlayer; and the group of external terminals connected to the wiringlayer, positioned within the region of the semiconductor chip and on thesupport substrate.
 18. A semiconductor device according to claim 16,wherein the group of terminals on the semiconductor chip are arranged inthe peripheral region of the circuit-formed surface of the semiconductorchip.
 19. A semiconductor device according to claim 17, wherein thegroup of terminals on the semiconductor chip is arranged in theperipheral region of the circuit-formed surface of the semiconductorchip.
 20. A wiring tape for a semiconductor device, which comprises awiring layer comprising an insulating layer and a wiring on theinsulating layer, one end of the wiring being connected to terminals onthe semiconductor chip and the other end of the wiring being connectedto external terminals for connecting to a package substrate; and athree-layered buffer layer bonded to the wiring-formed side of thewiring layer, the buffer layer comprising a structure havinginterconnected foams, an adhesive layer provided on the semiconductorchip-facing side of the structure having interconnected foams, directedto bonding to the semiconductor chip and another adhesive layer providedon the other side of the structure, directed to bonding to the wiringlayer.
 21. An adhesive tape according to claim 20, wherein a thicknessratio of the structure having interconnected foams to total buffer layeris at least 0.2.
 22. An adhesive tape according to claim 20, wherein thebuffer layer is composed of a laminate prepared by pasting both sides ofthe structure having interconnected foams with the adhesive layers,respectively.
 23. A wiring tape according to claim 20, wherein thebuffer layer is composed of a laminate prepared by pasting both sides ofthe structure having interconnected foams with adhesive layers eachcomprising a structure having interconnected foams whose pores arefilled with an adhesive, respectively.